The present invention relates generally to semiconductor device testing and, more particularly, to a method for specific site backside underlaying and micromasking for electrical characterization of semiconductor devices.
In the manufacture of semiconductor devices, the ability to obtain waveform measurements from internal nodes has been found to be critical to carrying out failure analysis and characterization. Often, active surfaces of the semiconductor devices are obscured by I/O (input/output) circuits, interconnect wiring, packaging, or limitations of the probing apparatus. During the integrated circuit development phase, early engineering hardware is typically characterized by subjecting the device to various test conditions such as speed, temperature, etc. Measuring and diagnosing the performance of these devices is done by acquiring waveforms from key circuit nodes within the device such as clock lines, enable signals, address buses, and data buses. If the early engineering hardware does not perform adequately, or is non-functional, it is critical to be able to trace back signals to the source of the problem. A convenient mode of detecting such failure source is by waveform analysis. The ability to diagnose problems by waveform analysis is also necessary during manufacture and throughout the life of the product so that corrective action can be taken.
Those skilled in the art will recognize that waveforms can be acquired from internal circuit nodes by direct-contact mechanical probing or electron beam probing. Additional techniques, such as laser-induced light, have also been reported. In order to prepare a device for diagnosis, it is necessary to establish electrical contact with a tester and one or more of the numerous I/O circuits in the device. In some instances, these I/O circuits are placed in the periphery of the device, or located in a manner to provide some degree of access to the device's active surface by some form of mechanical or electron beam probe during operation. However, as a result of increasing circuit complexity, a trend toward higher density packaging, or the density of the I/O circuits and related probes needed to activate the device, improvements in semiconductor device access for mechanical or electron beam probe are needed.
To facilitate electrical access to the I/O of the IC, additional circuits and pads are frequently positioned adjacent to, or on the uppermost level of the IC die. Quite frequently, such IC dies with I/O circuit elements situated on the top surface have the disadvantage of obstructing internal circuitry. Additionally, packaging methods, often referred to as a “flip-chip”, “C4”, or direct chip attach (DCA), can be attached upside-down, or flipped onto a package substrate, or directly onto a circuit board, flexible cable, or other assembly into which the IC is interconnected. As a result, the internal circuit nodes of the IC are buried and inaccessible for characterizing electrical circuit performance, performing diagnostic testing, or performing failure analysis while the IC is operating normally and in a fully functioning state.
In particular, with the emergence of technologies such as embedded dynamic random access memory (eDRAM), system on a chip (SOC), and silicon on insulator (SOI) devices, for example, effective backside electrical characterization techniques are desired given the multiple wiring levels of such devices.